Cache Memories for Dataflow Systems

Authors:
A. R. Hurson;Krishna M. Kavi;Behrooz Shirazi;Ben Lee
Affiliations:
-;-;-;-
Venue:
IEEE Parallel & Distributed Technology: Systems & Technology
Year:
1996

Citing 17
Cited 1

Locality, a memory hierarchy, and program restructuring in a dataflow environment

Journal of Systems and Software
Available instruction-level parallelism for superscalar and superpipelined machines

ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
An architecture of a dataflow single chip processor

ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Can dataflow subsume von Neumann computing?

ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results

ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The EPSILON-2 multiprocessor system

Journal of Parallel and Distributed Computing - Special issue: data-flow processing
A vertically layered allocation scheme for data flow systems

Journal of Parallel and Distributed Computing
Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Multithreading: a revisionist view of dataflow architectures

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Compiler-controlled multithreading for lenient parallel languages

Proceedings of the 5th ACM conference on Functional programming languages and computer architecture
Thread-based programming for the EM-4 hybrid dataflow machine

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
T: a multithreaded massively parallel architecture

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A high-speed memory organization for hybrid dataflow/von Neumann computing

Future Generation Computer Systems - Special issue: PARLE 91
Cache Memories for Data Flow Machines

IEEE Transactions on Computers
Design of cache memories for multi-threaded dataflow architecture

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Advanced Topics in Dataflow Computing and Multithreading

Advanced Topics in Dataflow Computing and Multithreading
Dataflow Architectures and Multithreading

Computer

Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation

Journal of VLSI Signal Processing Systems - special issue on multimedia signal processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

The dataflow model of computation, particularly the recent trend in combining dataflow processing with control-flow processing, provides attractive alternatives for designing new computer architectures. This marriage has also motivated researchers to analyze how to apply the familiar concepts within the framework of this new architectural model. The concept of cache memory has proven its effectiveness in the traditional control-flow architecture because of the spatial and temporal localities that govern the organization of the conventional programming environment. Therefore, the authors investigate the presence of localities in dataflow programs and analyze whether the cache can be incorporated into dataflow architectures. Addressing the application of cache memory in the dataflow environment, the authors compare the control-flow and dataflow programming environments, address previous work to incorporate cache in the dataflow computation, and discuss how to improve and detect locality in a dataflow program.