The Manchester prototype dataflow computer
Communications of the ACM - Special section on computer architecture
Implementation and evaluation of a list-processing-oriented data flow machine
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Evaluation of a prototype data flow processor of the SIGMA-1 for scientific computations
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Executing a program on the MIT tagged-token dataflow architecture
Volume II: Parallel Languages on PARLE: Parallel Architectures and Languages Europe
A unified resource management and execution control mechanism for data flow machines
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Incorporating data flow ideas into von neumann processors for parallel execution
IEEE Transactions on Computers
Toward a dataflow/von Neumann hybrid architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
MASA: a multithreaded processor architecture for parallel symbolic computing
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ACM Computing Surveys (CSUR)
On the working set concept for data-flow machines
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Instruction reference patterns in data flow programs
ACM '80 Proceedings of the ACM 1980 annual conference
Design of cache memories for multi-threaded dataflow architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Design of storage hierarchy in multithreaded architectures
Proceedings of the 28th annual international symposium on Microarchitecture
Cache Memories for Dataflow Systems
IEEE Parallel & Distributed Technology: Systems & Technology
| Hi-index | 14.98 |
Cache memories for dataflow machines are presented, and, in particular, four design principles for reducing the working set size of dataflow caches are introduced. They are (1) controlling the number of active state processes, (2) optimizing instruction addresses, (3) using a block-structured operand matching/waiting memory, and (4) making deterministic replacements. Based on these principles, instruction and operand caches are organized. A bypass control is also devised that enables cache block replacement to overlap with normal cache access. Miss ratio and performance of the caches are evaluated on a register transfer level simulator of a dataflow machine. The results show that the instruction cache of 1 k words and the operand cache of 2 k words achieve sufficiently low miss ratios. The bypass control compensates for the bandwidth of a narrow swapping channel to the extent that about eight dataflow processors with the caches can be integrated in an LSI chip.