Design of cache memories for multi-threaded dataflow architecture

Authors:
Krishna M. Kavi;A. R. Hurson;Phenil Patadia;Elizabeth Abraham;Ponnarasu Shanmugam
Affiliations:
The University of Texas at Arlington;The Pennsylvania, State University;The University of Texas at Arlington;The University of Texas at Arlington;The University of Texas at Arlington
Venue:
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Year:
1995

Citing 17
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Abstract

Cache memories have proven their effectiveness in the von Neumann architecture when localities of reference govern the execution loci of programs. A pure dataflow program, in contrast, contains no locality of reference since the execution sequence is enforced only by the availability of arguments. Instruction locality may be enhanced if, dataflow programs are reordered. Enhancing the locality of data references in the dataflow architecture is a more challenging problem. In this paper we report our approaches to the design of instruction, data (operand) and I-Structure cache memories using the Explicit Token Store (ETS) model of dataflow systems. We will present the performance results obtained using various benchmark programs.