Implementation and evaluation of a list-processing-oriented data flow machine
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Cache Memories for Data Flow Machines
IEEE Transactions on Computers
Design of cache memories for multi-threaded dataflow architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Design of storage hierarchy in multithreaded architectures
Proceedings of the 28th annual international symposium on Microarchitecture
Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation
IEEE Transactions on Computers - Special issue on the parallel architecture and compilation techniques conference
Amir Roth: Speculative Multithreaded Processors
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
An Efficient Way of Passing of Data in a Multithreaded Scheduled Dataflow Architecture
HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
A hybrid closed queuing network approach to model dataflow in networked distributed processors
Computer Communications
A closed queuing network model with multiple servers for multi-threaded architecture
Computer Communications
A hybrid closed queuing network model for multi-threaded dataflow architecture
Computers and Electrical Engineering
| Hi-index | 0.00 |
This paper presents a unified resource management and execution control mechanism for data flow machines. The mechanism integrates load control, depth-first execution control, cache memory control and a load balancing mechanism. All of these mechanisms are controlled by such basic information as the number of active state processes, Na. In data flow machines, synchronization among processes is an essential hardware function. Hence, Na can easily be detected by the hardware.Load control and depth-first execution control make it possible to execute a program with a designated degree of parallelism, and depth-first order. A cache memory of data flow processors in multiprocessing environments can be realized by using load and depth-first execution controls together with a deterministic replacement algorithm, i.e. replacement of only waiting state processes. A new load balancing method called group load balancing is also presented to evaluate the above mentioned mechanisms in multiprocessor environments.These unified control mechanisms are evaluated on a register transfer level simulator for a list-processing oriented data flow machine.