I-structures: data structures for parallel computing
ACM Transactions on Programming Languages and Systems (TOPLAS)
Analysis of multithreaded architectures for parallel computing
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Design of cache memories for multi-threaded dataflow architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
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Since long latency due to remote memory access could be tolerated by rapidly switching to another thread in multithreaded processing, caching I-structure data is expected to have less beneficial effect on the performance than caching ordinary data. In this paper, we show that caching I-structure data could improve the overall performance in spite of latency tolerating property of multithreading. Our quantitative analysis reveals that the most important caching effect of I-structure data in frame-based multithreading is the enhancement of frame parallelism. It reduces the idle time due to latency by lowering latency sensitivity and at the same time decreases the thread processing time by exploiting more processors.