Performance Impacts of Caching I-Structure Data on Frame-Based Multithreaded Processing

Authors:
Hyong-Shik Kim;Soonhoi Ha;Chu Shik Jhon
Affiliations:
-;-;-
Venue:
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
Year:
1997

Citing 4
Cited 1

I-structures: data structures for parallel computing

ACM Transactions on Programming Languages and Systems (TOPLAS)
Multithreading: a revisionist view of dataflow architectures

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Design of cache memories for multi-threaded dataflow architecture

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Performance Tradeoffs in Multithreaded Processors

IEEE Transactions on Parallel and Distributed Systems

Non-strict execution in parallel and distributed computing

International Journal of Parallel Programming

Quantified Score

Hi-index	0.00

Visualization

Abstract

Since long latency due to remote memory access or interprocessor communication could be tolerated in multithreaded processing, caching I-structure memory is expected to have less beneficial effect on the performance than caching ordinary data. In this paper, we suggest an organization and an operation scheme of an I-structure cache in frame-based multithreading, and show quantitatively that caching I-structure memory could improve the overall performance, in spite of the latency tolerating property of multithreading. With I-structure caches, the performance impacts are found three-fold: the reduction of average latency, the increase of quantum size, and the enhancement of frame parallelism. Among them, the enhancement of frame parallelism seems most important.