An effective on-chip preloading scheme to reduce data access penalty
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Stride directed prefetching in scalar processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Performance of a software MPEG video decoder
MULTIMEDIA '93 Proceedings of the first ACM international conference on Multimedia
Evaluating stream buffers as a secondary cache replacement
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
ACM Computing Surveys (CSUR)
Effective Hardware-Based Data Prefetching for High-Performance Processors
IEEE Transactions on Computers
Reuse of High Precision Arithmetic Hardware to Perform Multiple Low Precision Calculations
Reuse of High Precision Arithmetic Hardware to Perform Multiple Low Precision Calculations
RYO: a Versatile Instruction Instrumentation Tool for PA-RISC
RYO: a Versatile Instruction Instrumentation Tool for PA-RISC
Subword Parallelism with MAX-2
IEEE Micro
Architectural approaches for video compression
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Memory Performance Optimizations For Real-Time Software HDTV Decoding
Journal of VLSI Signal Processing Systems
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In this paper, we present a technique for improving the cache memory performance for software MPEG players. We motivate this technique by first presenting a characterization of cache behavior for mpeg\_play and mpeg2play MPEG applications. We then apply two hardware-based prefetching techniques to improve the cache memory performance. Previously published work has focused on applications of prefetching towards only scientific applications. The prefetching technique presented here eliminates approximately 80% of cache misses and potentially reduces execution time by a factor of two.