Systolic Opportunities for Multidimensional Data Streams
IEEE Transactions on Parallel and Distributed Systems
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Architectural approaches for video compression
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
A New Efficient Block-Matching Algorithm for Motion Estimation
Journal of VLSI Signal Processing Systems
Motion vector estimation using line-square search block matching algorithm for video sequences
EURASIP Journal on Applied Signal Processing
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Motion estimation is a very computational demanding operation during video compression process in standards such as MPEG4, thus special hardware architectures are required to achieve real-time compression performance. The present work focuses on the development of a reconfigurable systolic-based architecture implementing the Full Search Block Matching Algorithm (FBMA) which is highly computing-intensive and requires a large bandwidth to obtain real-time performance. The architecture comprises a smart memory scheme to reduce the number of accesses to data memory and Router elements to handle data movement among different structures inside the same architecture, adding the possibility of chaining interconnection of multiple processing blocks. Every Processing Element (PE) in the array includes a double ALU in order to search multiple macroblocks in parallel. The functionality has been extended to support operations involved in some other low-level image algorithms. Results show that a peak performance in the order of 9 GOPS can be achieved.