VLSI array processors
Optimal synthesis of control logic from behavioral specifications
Integration, the VLSI Journal
Vector quantization and signal compression
Vector quantization and signal compression
Architectural approaches for video compression
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
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We present parallel algorithms and array architectures for pyramidvector quantization (PVQ) [1] for use in image coding in low-power wirelesssystems. PVQ presents an alternative to other quantization methods which isespecially suitable for symmetric peer-to-peer communications likevideo-conferencing. But, both the encoding and decoding algorithms havedata-dependent iteration bounds and data-dependent dependencies whichprevent efficient parallelization of the algorithms for either hardware orsoftware implementations. We perform an algorithmic transformation [2] toconvert the data-dependent regular algorithms to equivalent data-independentalgorithms. The resulting regular algorithms exhibit modular and regularstructures with minimal control overhead; hence, they are well suited forVLSI array implementation in ASIC or FPGA technologies. Based on ourparallel algorithms and systematic design methodologies [3], we developlinear array architectures. Both encoder and decoder architectures consistof L identical processors with local interconnections and provide O(L)speed-up over a sequential implementation, where L is the dimension of avector. The architectures achieve 100% processor utilization andpermit power savings through early completion. A combined encoder-decoderarchitecture is also presented.