A survey of algorithms for volume visualization
ACM SIGGRAPH Computer Graphics
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Digital Image Processing
MPEG video decoding with the UltraSPARC visual instruction set
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
The visual instruction set (VIS) in UltraSPARC
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Advanced performance features of the 64-bit PA-8000
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
UltraSPARC-II: the advancement of ultracomputing
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Communications of the ACM
Optimizing the data cache performance of a software MPEG-2 video decoder
MULTIMEDIA '97 Proceedings of the fifth ACM international conference on Multimedia
A performance study of out-of-order vector architectures and short registers
ICS '98 Proceedings of the 12th international conference on Supercomputing
Vector architectures: past, present and future
ICS '98 Proceedings of the 12th international conference on Supercomputing
A bandwidth-efficient architecture for media processing
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Performance of image and video processing with general-purpose processors and media ISA extensions
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Adding a vector unit to a superscalar processor
ICS '99 Proceedings of the 13th international conference on Supercomputing
Exploiting a new level of DLP in multimedia applications
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
MOM: a matrix SIMD instruction set architecture for multimedia applications
SC '99 Proceedings of the 1999 ACM/IEEE conference on Supercomputing
Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
Polygon rendering on a stream architecture
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Exploiting superword level parallelism with multimedia instruction sets
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
ACM Transactions on Computer Systems (TOCS)
Efficient conditional operations for data-parallel architectures
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Broadband MPEG-2 Client with Network Configuration Capability
Multimedia Tools and Applications
A Vectorizing Compiler for Multimedia Extensions
International Journal of Parallel Programming
Video compression with parallel processing
Parallel Computing - Parallel computing in image and video processing
Reconfigurable media processing
Parallel Computing - Parallel computing in image and video processing
Subword Extensions for Video Processing on Mobile Systems
IEEE Concurrency
Efficient Polygon Clipping for an SIMD Graphics Pipeline
IEEE Transactions on Visualization and Computer Graphics
SH-5: The 64-Bit SuperH Architecture
IEEE Micro
Imagine: Media Processing with Streams
IEEE Micro
Measuring the Performance of Multimedia Instruction Sets
IEEE Transactions on Computers
Real-time stereo within the VIDET Project
Real-Time Imaging
Accelerating RBF Network Simulation by Using Multimedia Extensions of Modern Microprocessors
ICANN '01 Proceedings of the International Conference on Artificial Neural Networks
Performance of the Complex Streamed Instruction Set on Image Processing Kernels
Euro-Par '01 Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing
Performance Scalability of Multimedia Instruction Set Extensions
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Multimedia Extensions and Sub-word Parallelism in Image Processing: Preliminary Results
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Automatic SIMD Parallelization of Embedded Applications Based on Pattern Recognition
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Real-Time Layered Video Compression Using SIMD Computation
ParNum '99 Proceedings of the 4th International ACPC Conference Including Special Tracks on Parallel Numerics and Parallel Computing in Image Processing, Video Processing, and Multimedia: Parallel Computation
Recent Developments in the Design of Conventional Cryptographic Algorithms
State of the Art in Applied Cryptography, Course on Computer Security and Industrial Cryptography - Revised Lectures
Using Intel Streaming SIMD Extensions for 3D Geometry Processing
PCM '02 Proceedings of the Third IEEE Pacific Rim Conference on Multimedia: Advances in Multimedia Information Processing
Quantifying behavioral differences between multimedia and general-purpose workloads
Journal of Systems Architecture: the EUROMICRO Journal
Three-dimensional memory vectorization for high bandwidth media memory systems
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Architectural approaches for video compression
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Fast Subword Permutation Instructions Using Omega and Flip Network Stages
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
General-Purpose Processor Huffman Encoding Extension
ITCC '00 Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00)
Architectural techniques for accelerating subword permutations with repetitions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A high-speed energy-efficient 64-bit reconfigurable binary adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing
Journal of VLSI Signal Processing Systems
Reconfigurable universal SAD-multiplier array
Proceedings of the 2nd conference on Computing frontiers
The CSI multimedia architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accelerating Mobile Video: A 64-Bit SIMD Architecture for Handheld Applications
Journal of VLSI Signal Processing Systems
A PC-based real-time stereo vision system
Machine Graphics & Vision International Journal
Exploiting Vector Parallelism in Software Pipelined Loops
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Optimizing mobile multimedia using SIMD techniques
Multimedia Tools and Applications
Avoiding conversion and rearrangement overhead in SIMD architectures
International Journal of Parallel Programming
Quantized color instruction set for media-on-demand applications
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
Limitations of special-purpose instructions for similarity measurements in media SIMD extensions
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Versatility of extended subwords and the matrix register file
ACM Transactions on Architecture and Code Optimization (TACO)
Configurable data memory for multimedia processing
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
The Impact of Multimedia Extensions for Multimedia Applications on Mobile Computing Systems
APCHI '08 Proceedings of the 8th Asia-Pacific conference on Computer-Human Interaction
Parallel processing for image and video processing: Issues and challenges
Parallel Computing
Low-power mixed-signal CVNS-based 64-bit adder for media signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multi-streaming SIMD architecture for multimedia applications
Proceedings of the 6th ACM conference on Computing frontiers
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Multiplication acceleration through twin precision
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SHA: a design for parallel architectures?
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
A multi-streaming SIMD multimedia computing engine
Microprocessors & Microsystems
Parallel programming for multimedia applications
Multimedia Tools and Applications
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Color-Aware Instructions for Embedded Superscalar Processors
Journal of Signal Processing Systems
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Architectural enhancements for color image and video processing on embedded systems
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Algorithms and architectures for 2D discrete wavelet transform
The Journal of Supercomputing
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
ACM Transactions on Computer Systems (TOCS)
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The Visual Instruction Set (VIS), first introduced with the UltraSPARC-I microprocessor, is described from an Instruction Set Architecture (ISA) standpoint. Besides covering the functionality of each instruction individually, we look at a few widely used algorithms that can be sped up significantly (2-7X) by using VIS. The software environment surrounding VIS is also described.