Impact of multimedia extensions for different processing element granularities on an embedded imaging system

Authors:
Jong-Myon Kim
Affiliations:
School of Computer Engineering and Information Technology, University of Ulsan, Ulsan, South Korea
Venue:
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Year:
2010

Citing 10
Cited 0

Exploiting SIMD parallelism in DSP and multimedia algorithms using the AltiVec technology

ICS '99 Proceedings of the 13th international conference on Supercomputing
Heterogeneous architecture models for interconnect-motivated system design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
VIS Speeds New Media Processing

IEEE Micro
MMX Technology Extension to the Intel Architecture

IEEE Micro
Subword Parallelism with MAX-2

IEEE Micro
Implementing Streaming SIMD Extensions on the Pentium III Processor

IEEE Micro
Digital Image Processing (3rd Edition)

Digital Image Processing (3rd Edition)
Computer Architecture: Challenges and Opportunities for the Next Decade

IEEE Micro
Editorial: color in image and video processing

Journal on Image and Video Processing - Color in Image and Video Processing
A multi-streaming SIMD architecture for multimedia applications

Proceedings of the 6th ACM conference on Computing frontiers

Quantified Score

Hi-index	0.00

Visualization

Abstract

Multimedia applications are among the most dominant computing workloads driving innovations in high performance and cost effective systems In this regard, modern general-purpose microprocessors have included multimedia extensions (e.g., MMX, SSE, VIS, MAX, ALTIVEC) to their instruction set architectures to improve the performance of multimedia with little added cost to microprocessors Whereas prior studies of multimedia extensions have primarily focused on a single processor, this paper quantitatively evaluates the impact of multimedia extensions on system performance and efficiency for different number of processing elements (PEs) within an integrated multiprocessor array This paper also identifies the optimal PE granularity for the array system and implementation technology in terms of throughput, area efficiency, and energy efficiency using architectural and workload simulation Experimental results with cycle accurate simulation and technology modeling show that MMX-type instructions (a representative Intel's multimedia extensions) achieve an average speedup ranging from 1.24( (at a 65,536 PE system) to 5.65( (at a 4 PE system) over the baseline performance In addition, the MMX-enhanced processor array increases both area and energy efficiency over the baseline for all the configurations and programs Moreover, the highest area and energy efficiency are achieved at the number of PEs between 256 and 1,024 These evaluation techniques composed of performance simulation and technology modeling can provide solutions to the design challenges in a new class of multiprocessor array systems for multimedia.