The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Performance of image and video processing with general-purpose processors and media ISA extensions
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Flexible design of SPARC cores: a quantitative study
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
Exploiting superword level parallelism with multimedia instruction sets
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
Complete Guide to Mmx Technology
Complete Guide to Mmx Technology
VIS Speeds New Media Processing
IEEE Micro
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Automatic Architectural Synthesis of VLIW and EPIC Processors
Proceedings of the 12th international symposium on System synthesis
Scalable Processor Instruction Set Extension
IEEE Design & Test
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This paper presents the necessary steps to modify the implementation of the SPARCV8 architecture to enhance it with multimedia-oriented instructions. The purpose is improving video compression performance without designing dedicated coprocessors. We investigate the complexity of modifying a standard processor instruction set and show that, although not trivial, this is feasible in a few weeks. We implemented 12 new instructions and use some of them to optimize the computation of a demanding step of the MPEG encoding. The result is a performance increase of 67% in the execution of a part of this algorithm, allowing us to expect a 30% speedup in the execution of an MPEG video compression. The area increase of the integer unit is about 18% and the clock frequency is not significantly modified in an LEON-2 implementing 6 among 12 of the new instructions.