Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features
Journal of Electronic Testing: Theory and Applications
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
WCET analysis for a Java processor
JTRES '06 Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
IEEE Transactions on Computers
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique
Journal of Electronic Testing: Theory and Applications
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
A Hardware Acceleration Platform for Digital Holographic Imaging
Journal of Signal Processing Systems
Aspects in hardware: what do they look like?
Proceedings of the 2008 AOSD workshop on Aspects, components, and patterns for infrastructure software
Intel® atom™ processor core made FPGA-synthesizable
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Intel nehalem processor core made FPGA synthesizable
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Real-time fault injection using enhanced on-chip debug infrastructures
Microprocessors & Microsystems
Reliable software for unreliable hardware: embedded code generation aiming at reliability
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Towards a secure and reliable system
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Impact of faults in combinational logic of commercial microcontrollers
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Heterogeneous integration to simplify many-core architecture simulations
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Instruction scheduling for reliability-aware compilation
Proceedings of the 49th Annual Design Automation Conference
Selectively fortifying reconfigurable computing device to achieve higher error resilience
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Configurable fault-tolerance for a configurable VLIW processor
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Leveraging variable function resilience for selective software reliability on unreliable hardware
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting program-level masking and error propagation for constrained reliability optimization
Proceedings of the 50th Annual Design Automation Conference
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The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors tolerates transient SEU errors by using techniques such as TMR registers, on-chip EDAC, parity, pipeline restart, and forced cache miss. The first prototypes were manufactured on the Atmel ATC35 0.35 µm CMOS process, and subjected to heavy-ion fault-injection at the Louvain Cyclotron. The heavy-ion tests showed that all of the injected errors ( 100,000) were successfully corrected without timing or software impact. The device SEU threshold was measured to be below 6 MeV while ion energy-levels of up to 110 MeV were used for error injection.