Fault Injection for Dependability Validation: A Methodology and Some Applications
IEEE Transactions on Software Engineering
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
FINE: A Fault Injection and Monitoring Environment for Tracing the UNIX System Behavior Under Faults
IEEE Transactions on Software Engineering - Special issue on software reliability
FERRARI: A Flexible Software-Based Fault and Error Injection System
IEEE Transactions on Computers - Special issue on fault-tolerant computing
IBM experiments in soft fails in computer electronics (1978–1994)
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Electromigration: the time bomb in deep-submicron ICs
IEEE Spectrum
DEPEND: A Simulation-Based Environment for System Level Dependability Analysis
IEEE Transactions on Computers
Terrestrial cosmic ray intensities
IBM Journal of Research and Development
A Design Diversity Metric and Analysis of Redundant Systems
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
Embedded Robustness IPs for Transient-Error-Free ICs
IEEE Design & Test
FOCUS: An Experimental Environment for Fault Sensitivity Analysis
IEEE Transactions on Computers
Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers
IEEE Transactions on Software Engineering
RIFLE: A General Purpose Pin-level Fault Injector
EDCC-1 Proceedings of the First European Dependable Computing Conference on Dependable Computing
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
GOOFI: Generic Object-Oriented Fault Injection Tool
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
A Technique for Automated Validation of Fault Tolerant Designs Using Laser Fault Injection (LFI)
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
New Techniques for Accelerating Fault Injection in VHDL Descriptions
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Exploiting FPGA for Accelerating Fault Injection Experiments
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Dependability evaluation using hybrid fault/error injection
IPDS '95 Proceedings of the International Computer Performance and Dependability Symposium on Computer Performance and Dependability Symposium
DOCTOR: an integrated software fault injection environment for distributed real-time systems
IPDS '95 Proceedings of the International Computer Performance and Dependability Symposium on Computer Performance and Dependability Symposium
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
Journal of Electronic Testing: Theory and Applications
Efficient analysis of single event transients
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Soft Errors in Advanced Computer Systems
IEEE Design & Test
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment
Microprocessors & Microsystems
Rapid transient fault insertion in large digital systems
Microprocessors & Microsystems
Configurable fault-tolerance for a configurable VLIW processor
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
IVF: characterizing the vulnerability of microprocessor structures to intermittent faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An hybrid architecture to detect transient faults in microprocessors: an experimental validation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hi-index | 14.98 |
This paper presents a detailed analysis of the behavior of a novel, fault-tolerant, 32-bit embedded CPU when compared to a default (non fault-tolerant) implementation of the same processor, during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states, redundancy at the pipeline level and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, probability of fault manifestation and the behavior of latent faults.