An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
A prototype of a VHDL-based fault injection tool: description and application
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
Speeding-Up Fault Injection Campaigns in VHDL Models
SAFECOMP '00 Proceedings of the 19th International Conference on Computer Safety, Reliability and Security
MEFISTO-L: A VHDL-Based Fault Injection Tool for the Experimental Assessment of Fault Tolerance
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
Fault Injection Techniques and Tools for Embedded Systems
Fault Injection Techniques and Tools for Embedded Systems
Comparison of Physical and Software-Implemented Fault Injection Techniques
IEEE Transactions on Computers
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Journal of Electronic Testing: Theory and Applications
On the Proposition of an EMI-Based Fault Injection Approach
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Fault Injection Techniques and their Accelerated Simulation in SystemC
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
IEEE Transactions on Computers
Simulated fault injections and their acceleration in SystemC
Microprocessors & Microsystems
FPGA-Based Fault Injection into Synthesizable Verilog HDL Models
SSIRI '08 Proceedings of the 2008 Second International Conference on Secure System Integration and Reliability Improvement
Dependability assessment of by-wire control systems using fault injection
Journal of Systems Architecture: the EUROMICRO Journal
A Novel Simulation Fault Injection Method for Dependability Analysis
IEEE Design & Test
Modeling and Mitigating Transient Errors in Logic Circuits
IEEE Transactions on Dependable and Secure Computing
Study of the effects of SET induced faults on submicron technologies
DSNW '11 Proceedings of the 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops
An on-line soft error mitigation technique for control logic of VLIW processors
DFT '12 Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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This paper presents a technique for rapid transient fault injection, regarding the CPU time, to perform simulation-based fault-injection in complex System-on-Chip Systems (SoCs). The proposed approach can be applied to complex circuits, as it is not required to modify the top-level modules of a design; moreover, it is capable to inject a wide range of fault models in a design and finally a competitive reduction in terms of CPU time will be achieved. The root of our method is based on the usage of simulator-commands along with partial code modification techniques. To prove the efficiency of the proposed method, it has been implemented on two case studies, a pre-synthesized netlist of an AVR microcontroller from ATMEL and a post placed-and-routed Verilog netlist of a high performance reconfigurable processor in 90-nm UMC technology, Xentium processor from Recore Systems. Experimental results show that our technique is able to reduce the CPU time by a factor ranging from 27% to 67% compared with typical simulation-based fault-injection approaches and by a factor of 10% compared with rapid simulation-based techniques.