Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Embedding infrastructure IP for SOC yield improvement
Proceedings of the 39th annual Design Automation Conference
Reducing pin and area overhead in fault-tolerant FPGA-based designs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
Using embedded infrastructure IP for SOC post-silicon verification
Proceedings of the 40th annual Design Automation Conference
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
Journal of Electronic Testing: Theory and Applications
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
Proceedings of the 1st conference on Computing frontiers
Dynamic adaptation for fault tolerance and power management in embedded real-time systems
ACM Transactions on Embedded Computing Systems (TECS)
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors
Journal of Electronic Testing: Theory and Applications
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Proceedings of the 42nd annual Design Automation Conference
A New Hybrid Fault Detection Technique for Systems-on-a-Chip
IEEE Transactions on Computers
Performance driven reliable link design for networks on chips
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Reliability-aware data placement for partial memory protection in embedded processors
Proceedings of the 2006 workshop on Memory system performance and correctness
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Asynchronous transient resilient links for NoC
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Exploiting selective placement for low-cost memory protection
ACM Transactions on Architecture and Code Optimization (TACO)
Fault-tolerant semantic mappings among heterogeneous and distributed local ontologies
Proceedings of the 2nd international workshop on Ontologies and information systems for the semantic web
Intelligent robustness insertion for optimal transient error tolerance improvement in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Complement routing: A methodology to design reliable routing algorithm for Network on Chips
Microprocessors & Microsystems
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
System-level hardware-based protection of memories against soft-errors
Proceedings of the Conference on Design, Automation and Test in Europe
Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Checkpointing for the reliability of real-time systems with on-line fault detection
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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Shrinking process geometries will make it imperative for designers to start paying attention to transient-error protection. Self-correcting intelligence embedded in ICs protects electronic systems against such unpredictable and insidious errors. Infrastructure IPs that focus on transient faults are a leading type of self-correcting intelligence.