Experimental analysis of computer system dependability
Fault-tolerant computer system design
The Effect of Program Behavior on Fault Observability
IEEE Transactions on Computers
Embedded Robustness IPs for Transient-Error-Free ICs
IEEE Design & Test
On-Chip Cache Memory Resilience
HASE '98 The 3rd IEEE International Symposium on High-Assurance Systems Engineering
A Cache Error Propagation Model
PRFTS '97 Proceedings of the 1997 Pacific Rim International Symposium on Fault-Tolerant Systems
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
FPGA-Based Fault Injection for Microprocessor Systems
ATS '01 Proceedings of the 10th Asian Test Symposium
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
Journal of Electronic Testing: Theory and Applications
Increasing Register File Immunity to Transient Errors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Compiler-guided register reliability improvement against soft errors
Proceedings of the 5th ACM international conference on Embedded software
Cache size selection for performance, energy and reliability of time-constrained systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Simulation-Based Soft Error Estimation Methodology for Computer Systems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Soft error benchmarking of L2 caches with PARMA
Proceedings of the ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Characterizing the impact of soft errors on iterative methods in scientific computing
Proceedings of the international conference on Supercomputing
Soft error benchmarking of L2 caches with PARMA
ACM SIGMETRICS Performance Evaluation Review - Performance evaluation review
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Instruction and data caches are well known architectural solutions that allow significantly improving the performance of high-end processors. Due to their sensitivity to soft errors they are often disabled in safety critical applications, thus sacrificing performance for improved dependability. In this paper we report an accurate analysis of the effects of soft errors in the instruction and data caches of a soft core implementing the SPARC architecture. Thanks to an efficient simulation-based fault injection environment we developed, we are able to present in this paper an extensive analysis of the effects of soft errors on a processor running several applications under different memory configurations. The procedure we followed allows the precise computation of the processor failure rate when the cache is enabled even without resorting to expensive radiation experiments.