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Cache Memory Organization to Enhance the Yield of High Performance VLSI Processors
IEEE Transactions on Computers
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Proceedings of the Conference on Design, Automation and Test in Europe
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SRAM leakage reduction by row/column redundancy under random within-die delay variation
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ACM Transactions on Architecture and Code Optimization (TACO)
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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ACM Transactions on Embedded Computing Systems (TECS)
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ACM Transactions on Architecture and Code Optimization (TACO)
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This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolerated or by the rapid degradation of performance as the number of faults increases. In this paper, we present a new technique that overcomes these two problems. This technique uses a special Programmable Address Decoder (PAD) to disable faulty blocks and to re-map their references to healthy blocks. Simulation results show that the performance degradation of direct-mapped caches with PAD is smaller than the previous techniques. However, for set-associative caches, the overhead of PAD is primarily advantageous if a relatively large number of faults is to be tolerated. The area overhead was estimated at about 10% of the overall cache area for a hypothetical design and is expected to be less for actual designs. The access time overhead is negligible.