On the repair of redundant RAMs
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Selective cache ways: on-demand cache resource allocation
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ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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Proceedings of the 2006 international symposium on Low power electronics and design
Process variation aware cache leakage management
Proceedings of the 2006 international symposium on Low power electronics and design
Yield-Aware Cache Architectures
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
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ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
SRAM leakage reduction by row/column redundancy under random within-die delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage-aware redundancy for reliable sub-threshold memories
Proceedings of the 48th Design Automation Conference
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Traditionally, spare rows/columns have been used in two ways: either to replace too leaky cells to reduce leakage, or to substitute faulty cells to improve yield. In contrast, we first choose a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for SRAM transistors at design time to reduce leakage, and then substitute the resulting too slow cells by spare rows/columns. We show that due to within-die delay variation of SRAM cells only a few cells violate target timing at higher Vth or Tox; we carefully choose the Vth and Tox values such that the original memory timing-yield remains intact for a negligible extra delay. On a commercial 90nm process assuming 3% variation in SRAM cell delay, we obtained 47% leakage reduction by adding only 5 redundant columns at negligible area, dynamic power and delay costs.