ACM Computing Surveys (CSUR)
The case for the reduced instruction set computer
ACM SIGARCH Computer Architecture News
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Retrospective on high-level language computer architecture
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
An instruction fetch unit for a graph reduction machine
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Efficient (stack) algorithms for analysis of write-back and sector memories
ACM Transactions on Computer Systems (TOCS)
Switch-level delay models for digital MOS VLSI
25 years of DAC Papers on Twenty-five years of electronic design automation
Cache Memory Organization to Enhance the Yield of High Performance VLSI Processors
IEEE Transactions on Computers
Multiple vs. wide shared bus multiprocessors
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Machine organization of the IBM RISC System/6000 processor
IBM Journal of Research and Development
16-bit vs. 32-bit instructions for pipelined microprocessors
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Cache evaluation and the impact of workload choice
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Performance Implications of Tolerating Cache Faults
IEEE Transactions on Computers
Some applications of the implicit register reference
ACM SIGARCH Computer Architecture News
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
Experimental evaluation of on-chip microprocessor cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Architecture of SOAR: Smalltalk on a RISC
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A non-uniform cache architecture for low power system design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A cache-defect-aware code placement algorithm for improving the performance of processors
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
DEFCAM: A design and evaluation framework for defect-tolerant cache memories
ACM Transactions on Architecture and Code Optimization (TACO)
Salvaging chips with caches beyond repair
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Modeling the impact of permanent faults in caches
ACM Transactions on Architecture and Code Optimization (TACO)
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A cache was first used in a commercial computer in 1968,1 and researchers have spent the last 15 years analyzing caches and suggesting improvements. In designing a VLSI instruction cache for a RISC microprocessor we have uncovered four ideas potentially applicable to other VLSI machines. These ideas provide expansible cache memory, increased cache speed, reduced program code size, and decreased manufacturing costs. These improvements blur the habitual distinction between an instruction cache and an instruction fetch unit. The next four sections present the four architectural ideas, followed by a section on performance evaluation of each idea. We then describe the implementation of the cache and finally summarize the results.