MIPS RISC architecture
Analyzing computer architectures
Analyzing computer architectures
The impact of code density on instruction cache performance
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Instruction-processing optimization techniques for VLSI microprocessors
Instruction-processing optimization techniques for VLSI microprocessors
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Architecture of a VLSI instruction cache for a RISC
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
16-bit Vs. 32-bit Instructions for Pipelined Microprocessors
16-bit Vs. 32-bit Instructions for Pipelined Microprocessors
Embedded systems design for low energy consumption
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Evaluation of a high performance code compression method
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
SH3: High Code Density, Low Power
IEEE Micro
IEEE Micro
IEEE Micro
M32R/D-Integrating DRAM and Microprocessor
IEEE Micro
SH-5: The 64-Bit SuperH Architecture
IEEE Micro
Reordering Memory Bus Transactions for Reduced Power Consumption
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Efficient code size reduction without performance loss
Proceedings of the 2007 ACM symposium on Applied computing
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
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In any stored-program computer system, information is constantly transferred between the memory and the instruction processor. Machine instructions are a major portion of this traffic. Since transfer bandwidth is a limited resource, inefficiency in the encoding of instruction information (low code density) can have definite hardware and performance costs.Starting with a parameterized baseline RISC design, we compare performance for two instruction encodings for the same instruction processing core. One is a variant of DLX, a typical 32-bit RISC instruction set. The other is a 16-bit format which sacrifices some expressive power while retaining essential RISC features. Using optimizing compilers and software simulation, we measure code density and path length for a suite of benchmark programs, relating performance differences to specific instruction set features. We measure time to completion performance while varying memory latency and instruction cache size parameters. The 16-bit format is shown to have significant cost-performance advantages over the 32-bit format under typical memory system performance constraints.