16-bit vs. 32-bit instructions for pipelined microprocessors
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder
Proceedings of the 6th international workshop on Hardware/software codesign
IMEM: an intelligent memory for bump- and reflection-mapping
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
A performance comparison of contemporary DRAM architectures
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Evaluation of processor code efficiency for embedded systems
ICS '01 Proceedings of the 15th international conference on Supercomputing
Energy-performance trade-offs for spatial access methods on memory-resident data
The VLDB Journal — The International Journal on Very Large Data Bases
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework
IEEE Transactions on Computers
Architectural Support for Data-intensive Applications
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Experimental Evaluation of Energy Behavior of Iteration Space Tiling
LCPC '00 Proceedings of the 13th International Workshop on Languages and Compilers for Parallel Computing-Revised Papers
Intelligent memory manager: reducing cache pollution due to memory management functions
Journal of Systems Architecture: the EUROMICRO Journal
Destructive-read in embedded DRAM, impact on power consumption
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Cache write-back schemes for embedded destructive-read DRAM
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Hardware/software tradeoffs for IP-over-ATM frame reassembly in an integrated architecture
Computer Communications
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Since the invention of the integrated circuit, many systems have been implemented by using IC, LSI and VLSI technologies. The design objective has been to realize systems which have high performance, high reliability, low power dissipation and low cost. Despite the rapid progress of semiconductor technology for microprocessors, logic, and DRAM, the integration of DRAM and processor has not been realized so far. This paper describes the implementation of a 32-bit RISC processor with embedded DRAM on one chip. This provides a high performance system component with low power dissipation, in other words, low processing energy components. In addition, this design provides the system designer with great flexibility. For example, JPEG decoding of full VGA can be realized in less than 0.5 sec by software using this chip, so that designers may eliminate the JPEG hardware module from a system.