Evaluation of processor code efficiency for embedded systems

  • Authors:

  • Morgan Hirosuke Miki;Mamoru Sakamoto;Shingo Miyamoto;Yoshinori Takeuchi;Toyohiko Yoshida;Isao Shirakawa

  • Affiliations:

  • Graduate School of Engineering, Osaka University, 2-1 Yamada-Oka, Suita, Osaka, 565-0871 Japan;System LSI Development, Center, Mitsubishi Electric, Corporation, 4-1 Mizuhara, Itami, Hyogo, 664-8641 Japan;Graduate School of Engineering, Osaka University, 2-1 Yamada-Oka, Suita, Osaka, 565-0871 Japan;Graduate School of Engineering Science, Osaka University, 1-3 Machikaneyama, Toyonaka, Osaka, 560-8531, Japan;Mobile Communication, Business Division, Mitsubishi, Electric Corporation, 8-1-1 Tsukaguchi-Honmachi, Amagasaki , Hyogo, 661-8661, Japan;Graduate School of Engineering, Osaka University, 2-1 Yamada-Oka, Suita, Osaka, 565-0871 Japan

  • Venue:
  • ICS '01 Proceedings of the 15th international conference on Supercomputing
  • Year:
  • 2001

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper evaluates the code efficiency of the ARM, Java, and x86 instruction sets by compiling the SPEC CPU95/ CPU2000/JVM98 and CaffeineMark benchmarks, in terms of code sizes, basic block sizes, instruction distributions, and average instruction lengths.As a result, mainly because (i) the Java architecture is a stack machine, (ii) there are only four local variables which can be accessed by a 1-byte instruction, and (iii) additional instructions are provided for the network security, the code efficiency of Java turns out to be inferior to that of ARM Thumb. Moreover, through this efficiency analysis it should be claimed that a more efficient code architecture can be constructed by taking minute account of the customization of an instruction set as well as the number of registers.