Cache write-back schemes for embedded destructive-read DRAM

Authors:
Haakon Dybdahl;Marius Grannæs;Lasse Natvig
Affiliations:
Department of Computer and Information Science, Faculty of Information Technology, Mathematics and Electrical Engineering, Norwegian University of Science and Technology;Department of Computer and Information Science, Faculty of Information Technology, Mathematics and Electrical Engineering, Norwegian University of Science and Technology;Department of Computer and Information Science, Faculty of Information Technology, Mathematics and Electrical Engineering, Norwegian University of Science and Technology
Venue:
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Year:
2006

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Abstract

Much of the chip area and power in a modern processor are used by mechanisms that compensate for slow main memory such as caches, out-of-order execution and prefetching. We attack this problem by utilizing a DRAM macro made by Hwang et. al that is faster than conventional DRAM macros, but does not conserve data in the DRAM cells after reading. Their prototype included a large write-back buffer for conserving data without degrading performance of read accesses. We eliminate this buffer by utilizing the already existing cache in processor designs at the cost of potential memory bank congestion. Two implementable and one theoretic upper-bound scheme for cache write-back are evaluated. We find that the size of the cache can be highly reduced without degrading performance when utilizing destructive-read DRAM. The large write-back buffer can be omitted when destructive-read DRAM is used with a processor with cache without significant degradation of performance.