Branch strategy taxonomy and performance models
Branch strategy taxonomy and performance models
16-bit vs. 32-bit instructions for pipelined microprocessors
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Instruction-level parallel processing: history, overview, and perspective
The Journal of Supercomputing - Special issue on instruction-level parallelism
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
SH3: High Code Density, Low Power
IEEE Micro
VIS Speeds New Media Processing
IEEE Micro
SH4 RISC Multimedia Microprocessor
IEEE Micro
Scheduling of synchronous data flow models on scratchpad memory based embedded processors
Proceedings of the International Conference on Computer-Aided Design
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Embodying an emerging philosophy of embedded-core design, the latest SuperH microprocessor provides a platform for a wide range of multimedia applications. Its SIMD extensions provide the parallelism required for efficient execution of these applications.