A multiple floating point coprocessor architecture
ACM SIGARCH Computer Architecture News
Fast breakpoints: design and implementation
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
The Design of a Microsupercomputer
Computer - Special issue on experimental research in computer architecture
A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1
Computer - Special issue on experimental research in computer architecture
Reducing the branch penalty by rearranging instructions in a double-width memory
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
High level synthesis of pipelined instruction set processors and back-end compilers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Circular scheduling: a new technique to perform software pipelining
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
On the potential of asynchronous pipelined processors
ACM SIGARCH Computer Architecture News
Viewing instruction set design as an optimization problem
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Improved multithreading techniques for hiding communication latency in multiprocessors
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Memory latency effects in decoupled architectures with a single data memory module
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Unboxed objects and polymorphic typing
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Tolerating data access latency with register preloading
ICS '92 Proceedings of the 6th international conference on Supercomputing
Eliminating the address translation bottleneck for physical address cache
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
A language-based approach to protocol implementation
SIGCOMM '92 Conference proceedings on Communications architectures & protocols
Balanced scheduling: instruction scheduling when memory latency is uncertain
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Register relocation: flexible contexts for multithreading
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
A case for two-way skewed-associative caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
16-bit vs. 32-bit instructions for pipelined microprocessors
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
A RISC processor architecture with a versatile stack system
ACM SIGARCH Computer Architecture News - Special issue on input/output in parallel computer systems
The effectiveness of decoupling
ICS '93 Proceedings of the 7th international conference on Supercomputing
The impact of operating system structure on memory system performance
SOSP '93 Proceedings of the fourteenth ACM symposium on Operating systems principles
Protocol service decomposition for high-performance networking
SOSP '93 Proceedings of the fourteenth ACM symposium on Operating systems principles
A language-based approach to protocol implementation
IEEE/ACM Transactions on Networking (TON)
Division by invariant integers using multiplication
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
Cache performance of garbage-collected programs
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
ACM SIGARCH Computer Architecture News
A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Avoiding conflict misses dynamically in large direct-mapped caches
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
A tool for processor instruction set design
EURO-DAC '94 Proceedings of the conference on European design automation
Unconstrained speculative execution with predicated state buffering
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Relocating machine instructions by currying
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Performance comparison of ILP machines with cycle time evaluation
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
An extendable MIPS-I processor kernel in VHDL for hardware/software co-design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Concurrent Detection of Software and Hardware Data-Access Faults
IEEE Transactions on Computers
A multiple floating point coprocessor architecture
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
MetaCore: an application specific DSP development system
DAC '98 Proceedings of the 35th annual Design Automation Conference
A time complexity lower bound for randomized implementations of some shared objects
PODC '98 Proceedings of the seventeenth annual ACM symposium on Principles of distributed computing
Trace-driven simulations for a two-level cache design in open bus systems
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The TLB slice—a low-cost high-speed address translation mechanism
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Speeding up power estimation of embedded software
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
A Processor Architecture for 3D Graphics
IEEE Computer Graphics and Applications
Microprocessor Memory Management Units
IEEE Micro
Compiling C on a Multiple-Stack Architecture
IEEE Micro
Branch Target Buffer Design and Optimization
IEEE Transactions on Computers
An Optimal Graph-Construction Approach to Placing Program Signatures for Signature Monitoring
IEEE Transactions on Computers
False Sharing and Spatial Locality in Multiprocessor Caches
IEEE Transactions on Computers
Faster Numerical Algorithms Via Exception Handling
IEEE Transactions on Computers
Memory Latency Effects in Decoupled Architectures
IEEE Transactions on Computers
A transformational approach to binary translation of delayed branches
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formally Verifying Data and Control with Weak Reachability Invariants
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Energy-exposed instruction sets
Power aware computing
PEAS-III: An ASIP Design Environment
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Compressing MIPS code by multiple operand dependencies
ACM Transactions on Embedded Computing Systems (TECS)
Fast breakpoints: design and implementation
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Balanced scheduling: instruction scheduling when memory latency is uncertain
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Code compression by register operand dependency
Journal of Systems and Software
Performance Models for Network Processor Design
IEEE Transactions on Parallel and Distributed Systems
Implementing virtual memory in a vector processor with software restart markers
Proceedings of the 20th annual international conference on Supercomputing
Cibyl: an environment for language diversity on mobile devices
Proceedings of the 3rd international conference on Virtual execution environments
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A One's Complement Cache Memory
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Lottery scheduling: flexible proportional-share resource management
OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
Using continuations to build a user-level threads library
MSYM'93 Proceedings of the 3rd conference on USENIX MACH III Symposium - Volume 1
Superscalar out-of-order demystified in four instructions
WCAE '03 Proceedings of the 2003 workshop on Computer architecture education: Held in conjunction with the 30th International Symposium on Computer Architecture
Improving SDRAM access energy efficiency for low-power embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Reconfigurable solutions for very-long arithmetic with applications in cryptography
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Revisiting Cache Block Superloading
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
A transformational approach to binary translation of delayed branches with applications to SPARC® and PA-RISC instructions sets
Evaluating the performance of space plasma simulations using FPGA's
VECPAR'02 Proceedings of the 5th international conference on High performance computing for computational science
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
Proceedings of the 37th annual international symposium on Computer architecture
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TOAST: applying answer set programming to superoptimisation
ICLP'06 Proceedings of the 22nd international conference on Logic Programming
Processor design using a functional hardware description language
Microprocessors & Microsystems
Journal of Parallel and Distributed Computing
| Hi-index | 0.02 |