Computer
How many addressing modes are enough?
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
MIPS RISC architecture
Supporting reference and dirty bits in SPUR's virtual address cache
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Computer programming and architecture: The VAX
Computer programming and architecture: The VAX
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Virtual memory primitives for user programs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The TLB slice—a low-cost high-speed address translation mechanism
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Design and Evaluation of In-Cache Address Translation
Design and Evaluation of In-Cache Address Translation
Aspects of Cache Memory and Instruction
Aspects of Cache Memory and Instruction
Consistency management for virtually indexed caches
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Address space sparsity and fine granularity
ACM SIGOPS Operating Systems Review
High-bandwidth address translation for multiple-issue processors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Locality As a Visualization Tool
IEEE Transactions on Computers
Functional Implementation Techniques for CPU Cache Memories
IEEE Transactions on Computers - Special issue on cache memory and related problems
Address space sparsity and fine granularity
EW 6 Proceedings of the 6th workshop on ACM SIGOPS European workshop: Matching operating systems to application needs
IEEE Transactions on Computers
Generating physical addresses directly for saving instruction TLB energy
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
U-cache: a cost-effective solution to synonym problem
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Caches versus object allocation
IWOOOS '96 Proceedings of the 5th International Workshop on Object Orientation in Operating Systems (IWOOOS '96)
Highly accurate and efficient evaluation of randomising set index functions
Journal of Systems Architecture: the EUROMICRO Journal
Compiler-directed code restructuring for reducing data TLB energy
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Optimizing instruction TLB energy using software and hardware techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware/software approaches for reducing the process variation impact on instruction fetches
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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