Virtual memory primitives for user programs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Lightweight shared objects in a 64-bit operating system
OOPSLA '92 conference proceedings on Object-oriented programming systems, languages, and applications
Eliminating the address translation bottleneck for physical address cache
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Architecture support for single address space operating systems
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Protection traps and alternatives for memory management of an object-oriented language
SOSP '93 Proceedings of the fourteenth ACM symposium on Operating systems principles
A Micro-Kernel Architecture for Next Generation Processor
Proceedings of the Workshop on Micro-kernels and Other Kernel Architectures
Guarded page tables on Mips R4600 or an exercise in architecture-dependent micro optimization
ACM SIGOPS Operating Systems Review
Accelerating two-dimensional page walks for virtualized systems
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Multi-compartment: a new architecture for secure co-hosting on SoC
SOC'09 Proceedings of the 11th international conference on System-on-chip
Translation caching: skip, don't walk (the page table)
Proceedings of the 37th annual international symposium on Computer architecture
SpecTLB: a mechanism for speculative address translation
Proceedings of the 38th annual international symposium on Computer architecture
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To fully exploit the potential of large address spaces, e.g. 264-byte, the sparsity problem has to be solved in an efficient manner. Current address translation schemes either cause enormous space overhead (page table trees) or do not support address space structuring, object grouping and mixed page sizes (inverted page tables), Furthermore, an essential handicap of current virtual address spaces is their coarse granularity. It restricts the concept's relevance to low level OS technology. Without this constraint, mapping could be a vertically integrating paradigm, useful on all levels from hardware up to application programming.Guarded page tables help solving both problems. They permit significant extensions of the current programming model without performance degradation: sparse occupation and coarse-grain (4K) pages can be handled by purely conventional hardware; fine-grain (down to 16-byte) pages without fine-grain aliasing become also possible using conventional cache and TLB technology combined with stochastically colored allocation. Unrestricted aliasing and unlimited user level mapping without performance degradation may become possible by hardware innovation.