Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
MIPS RISC architecture
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Communications of the ACM
Partial evaluation and automatic program generation
Partial evaluation and automatic program generation
Rewriting executable files to measure program behavior
Software—Practice & Experience
Steps towards mechanizing program transformations using PVS
Science of Computer Programming - Special issue on mathematics of program construction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Specifying representations of machine instructions
ACM Transactions on Programming Languages and Systems (TOPLAS)
JiTI: a robust just in time instrumentation technique
ACM SIGARCH Computer Architecture News
Design and Analysis of Instruction Set Processors
Design and Analysis of Instruction Set Processors
Machine Descriptions to Build Tools for Embedded Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
The Design of a Resourceable and Retargetable Binary Translator
WCRE '99 Proceedings of the Sixth Working Conference on Reverse Engineering
Assembly to High-Level Language Translation
ICSM '98 Proceedings of the International Conference on Software Maintenance
Computer structures: Readings and examples (McGraw-Hill computer science series)
Computer structures: Readings and examples (McGraw-Hill computer science series)
A transformational approach to binary translation of delayed branches with applications to SPARC® and PA-RISC instructions sets
Experience in the design, implementation and use of a retargetable static binary translation framework
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Building the world from first principles: declarative machine descriptions and compiler construction
PADL'05 Proceedings of the 7th international conference on Practical Aspects of Declarative Languages
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A binary translator examines binary code for a source machine and generates code for a target machine. Understanding what to do with delayed branches in binary code can involve tricky case analyses, for example, if there is a branch instruction in a delay slot. This article presents a disciplined method for deriving such case analyses. The method identifies problematic cases, shows the translations for the nonproblematic cases, and gives confidence that all cases are considered. The method supports such common architectures as SPARC, MIPS, and PA-RISC, and it should apply to any tool that analyzes machine instructions. We begin by writing a very simple interpreter for the source machine's code. We then transform the interpreter into an interpreter for a target machine without delayed branches. To maintain the semantics of the program being interpreted, we simultaneously transform the sequence of source-machine instructions into a sequence of target-machine instructions. The transformation of the instructions becomes our algorithm for binary translation.