MIPS RISC architecture
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
High level synthesis of pipelined instruction set processors and back-end compilers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Architecture synthesis of high-performance application-specific processors
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Scheduling for functional pipelining and loop winding
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Application-driven design automation for microprocessor design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis of pipelined instruction set processors
DAC '93 Proceedings of the 30th international Design Automation Conference
Prophetic branches: a branch architecture for code compaction and efficient execution
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ACM Computing Surveys (CSUR)
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Improving the throughput of a pipeline by insertion of delays
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
The performance impact of incomplete bypassing in processor pipelines
Proceedings of the 28th annual international symposium on Microarchitecture
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