A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
The white dwarf: a high-performance application-specific processor
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Organization of array data for concurrent memory access
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Run-time disambiguation: coping with statically unpredictable dependencies
IEEE Transactions on Computers
Selected papers of the second workshop on Languages and compilers for parallel computing
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A global resource-constrained parallelization technique
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
High level synthesis of pipelined instruction set processors and back-end compilers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Implementation optimization techniques for architecture synthesis of application-specific processors
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Generating instruction sets and microarchitectures from applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Global scheduling for high-level synthesis applications
DAC '94 Proceedings of the 31st annual Design Automation Conference
A register file and scheduling model for application specific processor synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A methodology and algorithms for the design of hard real-time multitasking ASICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
High-level automatic pipelining for sequential circuits
Proceedings of the 14th international symposium on Systems synthesis
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
| Hi-index | 0.00 |
The key principles of the Application-Specific Processor Design (ASPD) methodology include: a semi-custom compilation-driven design/implementation approach, the exploitation of fine-grained parallelism for high performance, and the adaptation of datapath topology to the data transfers required by the application. The powerful microcode compilation techniques of Percolation Scheduling and Pipeline Scheduling extract and enhance the parallelism in the application object code to generate an optimized specification of the target processor. Implementation optimization is performed to allocate functional units and register files. Graph-coloring algorithms minimize the amount of hardware needed to exploit available parallelism. Data memory employs an organization with multiple banks. Compilation techniques are used to allocate data over the memory banks to enhance parallel access.