A register file and scheduling model for application specific processor synthesis

PLD: digital system design using programmable logic devices

PLD: digital system design using programmable logic devices

Architecture synthesis of high-performance application-specific processors

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference

Register allocation for software pipelined loops

PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation

Code generation schema for modulo scheduled loops

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture

Rotation scheduling: a loop pipelining algorithm

DAC '93 Proceedings of the 30th international Design Automation Conference

A VHDL-based design methodology: the design experience of a high performance ASIC chip

EURO-DAC '94 Proceedings of the conference on European design automation

Consumer Applications: A Driving Force for High-Level Synthesis of Signal-Processing Architectures

IEEE Micro