A register file and scheduling model for application specific processor synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
ECBS '96 Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems
Reconfigurable Fast Memory Management System Design for Application Specific Processors
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Custom Processor Core Construction from C Code
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
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In all application domains of multimedia, communication and network processing where huge amount of data processing at desired performance and power consumption are a mandatory prerequisite for successful functioning; the system architects have to find a design that fulfills the user requirements of the optimization parameters, while minimizing the cost as much as possible. In this paper a novel FPGA based comparative analysis to compare the cost-performance ratio (CPR) of an Application Specific Processor (ASP) with Microblaze soft core RISC processor is proposed. The paper also proposes an exclusive performance assessment between the FPGA based ASP and Microblaze soft core RISC processor embedded in FPGA. The paper also highlights the design processes of a performance optimized power stringent ASP by converting a computation intensive application into an actual Register Transfer Level (RTL) hardware design as well as the Microblaze soft core RISC processor for a same given application. The experimental results of the FPGA based speedup analysis indicated that for 'N' sets of processed data, the application specific processor performs faster than RISC. Further, it was concluded that speedup of ASP increases proportionally with increase in number of processed data. Moreover, the results of CPR comparison indicated that as the number of units of production increases, the value of CPR for the ASP becomes larger compared to CPR of RISC processor.