Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Knowledge based control in micro-architecture design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Synthesis by delayed binding of decisions
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Synthesis of VLSI systems with the CAMAD design aid
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
PLEST: a program for area estimation of VLSI integrated circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An Artificial Intelligence Approach to VLSI Design
An Artificial Intelligence Approach to VLSI Design
A method of automatic data path synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
Register-transfer level digital design automation: The allocation process
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '78 Proceedings of the 15th Design Automation Conference
Automated exploration of the design space for register-transfer (rt) systems.
Automated exploration of the design space for register-transfer (rt) systems.
Synthesis of digital designs from recursion equations
Synthesis of digital designs from recursion equations
Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
LASSIE: structure to layout for behavioral synthesis tools
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
ACE: a hierarchical graphical interface for architectual synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VHDL synthesis using structured modeling
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An intermediate representation for behavioral synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Global hardware synthesis from behavioral dataflow descriptions
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Architecture synthesis of high-performance application-specific processors
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Abstract data types and high-level synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Automated micro-roll-back self-recovery synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Bottom up synthesis based on fuzzy schedules
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Distributed design-space exploration for high-level synthesis systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Deriving efficient area and delay estimates by modeling layout tools
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the use of VHDL-based behavioral synthesis for telecom ASIC design
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A recursive technique for computing lower-bound performance of schedules
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hierarchical behavioral partitioning for multicomponent synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Storage optimization by replacing some flip-flops with latches
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Code generation for a DSP processor
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Constraint analysis for DSP code generation
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Proceedings of the 11th international symposium on System synthesis
An efficient multi-view design model for real-time interactive synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A constraint driven approach to loop pipelining and register binding
Proceedings of the conference on Design, automation and test in Europe
An RTL design-space exploration method for high-level applications
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Constraint analysis for DSP code generation
Readings in hardware/software co-design
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
1988 Design Automation Conference: Guest Editorial
IEEE Design & Test
The V Compiler: Automatic Hardware Design
IEEE Design & Test
Algorithms for High-Level Synthesis
IEEE Design & Test
From Behavior to Structure: High-Level Synthesis
IEEE Design & Test
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Using Feedback to Improve VLSI Designs
IEEE Expert: Intelligent Systems and Their Applications
High-level synthesis for easy testability
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Synchronous Controller Models for Synthesis from Communicating VHDL Processes
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A new approach to pipeline optimisation
EURO-DAC '90 Proceedings of the conference on European design automation
System synthesis using behavioural descriptions
EURO-DAC '90 Proceedings of the conference on European design automation
Towards a global solution to high level synthesis problems
EURO-DAC '90 Proceedings of the conference on European design automation
A design representation for high level synthesis
EURO-DAC '90 Proceedings of the conference on European design automation
Correct interactive transformational synthesis of DSP hardware
EURO-DAC '91 Proceedings of the conference on European design automation
Specification of timing constraints for controller synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Improved force-directed scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Co-evolutionary high-level test synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Design methodologies and CAD tools
Integration, the VLSI Journal
A unified approach for scheduling and allocation
Integration, the VLSI Journal
Path-based scheduling in a hardware compiler
Proceedings of the Conference on Design, Automation and Test in Europe
MULTIPAR: behavioral partition for synthesizing multiprocessor architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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High-level synthesis takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. In this tutorial we will examine the high-level synthesis task, showing how it can be decomposed into a number of distinct but not independent subtasks. Then we will present the techniques that have been developed for solving those subtasks. Finally, we will note those areas related to high-level synthesis that are still open problems.