A computational logic handbook
A computational logic handbook
ACE: a hierarchical graphical interface for architectual synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Behavior-preserving transformations for high-level synthesis
Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Fm8501: a verified microprocessor (theorem-proving, computers, design)
Fm8501: a verified microprocessor (theorem-proving, computers, design)
Formal verification of behavioral VHDL specifications: a case study
EURO-DAC '94 Proceedings of the conference on European design automation
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We present a new interactive tool for the guided synthesis of digital signal processing hardware. The tool is driven from a HDL. It will suggest different ways of implementing different architectures for the same specification, maintaining the correctness of implementations during the design process. The tool will automatically generate input for the Boyer Moore theorem prover from the HDL specification in order to verify the correctness of the implementations.