An Automaton Model for Scheduling Constraints in Synchronous Machines
IEEE Transactions on Computers
From VHDL to efficient and first-time-right designs: a formal approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Equivalent design representations and transformations for interactive scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An algorithm to determine mutually exclusive operations in behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
On the fundamental limitations of transformational design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
From Behavior to Structure: High-Level Synthesis
IEEE Design & Test
Formal Synthesis at the Algorithmic Level
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
An HOL based framework for design of correct high level synthesizers
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Redesign using state splitting
EURO-DAC '90 Proceedings of the conference on European design automation
Correct interactive transformational synthesis of DSP hardware
EURO-DAC '91 Proceedings of the conference on European design automation
Automatic generation of equivalent architecture model from functional specification
Proceedings of the 41st annual Design Automation Conference
A formalism for functionality preserving system level transformations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Verification of system level model transformations
International Journal of Parallel Programming
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