Data structures and network algorithms
Data structures and network algorithms
Communicating sequential processes
Communicating sequential processes
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Behavior-preserving transformations for high-level synthesis
Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects
The FSM network model for behavioral synthesis of control-dominated machines
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The Princeton University behavioral synthesis system
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High level synthesis and generating FPGAs with the BEDROC system
Journal of VLSI Signal Processing Systems - Special issue on field-programmable gate arrays
Scheduling constraint generation for communicating processes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HERCULES—a system for high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Communication and Concurrency
Logic Design of Digital Systems
Logic Design of Digital Systems
VHDL, Hardware Description and Design
VHDL, Hardware Description and Design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
A Formally Verified System for Logic Synthesis
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Automated High-level Verification Against Clocked Algorithmic Specifications
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
The Princeton University behavioral synthesis system
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Scheduling a minimum dependence in FSMs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Redundancy Removal during High-Level Synthesis Using Scheduling Don‘t-Cares
Journal of Electronic Testing: Theory and Applications
Hardware/software synthesis of formal specifications in codesign of embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automata-Based Symbolic Scheduling for Looping DFGs
IEEE Transactions on Computers
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
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We present a finite-state model for scheduling constraints in digital system design. We define a two-level hierarchy of finite-state machines: a behavior FSM's input and output events are partially ordered in time; a register-transfer FSM is a traditional FSM whose inputs and outputs are totally ordered in time. Explicit modeling of scheduling constraints is useful for both high-level synthesis and verification-we can explicitly search the space of register-transfer FSM's which implement a desired schedule. State-based models for scheduling are particularly important in the design of control-dominated systems. This paper describes the BFSM I model, describes several important operations and algorithms on BFSM's and networks of communicating BFSM's, and illustrates the use of BFSM's in high-level synthesis