Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An Automaton Model for Scheduling Constraints in Synchronous Machines
IEEE Transactions on Computers
Scheduling and binding bounds for RT-level symbolic execution
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient encoding for exact symbolic automata-based scheduling
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A model for scheduling protocol-constrained components and environments
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A code-motion pruning technique for global scheduling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Time-Constrained Loop Pipelining
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Symbolic scheduling techniques
Symbolic scheduling techniques
Automata-based symbolic scheduling
Automata-based symbolic scheduling
A new approach to pipeline optimisation
EURO-DAC '90 Proceedings of the conference on European design automation
A new symbolic technique for control-dependent scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scheduling and control generation with environmental constraints based on automata representations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Rotation scheduling: a loop pipelining algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wavesched: a novel scheduling technique for control-flow intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level DSP synthesis using concurrent transformations, scheduling, and allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symbolic NFA scheduling of a RISC microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Representing and Scheduling Looping Behavior Symbolically
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Coordinated resource optimization in behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
| Hi-index | 14.98 |
This paper presents an exact technique for scheduling looping data-flow graphs that implicitly supports functional pipelining and loop winding. Automata-based symbolic modeling provides efficient representation of all causal executions of a given behavioral description subject to finite state bounds. Since a complete set of scheduling solutions is found, further incremental refinements, such as sequential interface protocol constraints, can be easily accommodated. Efficiency in the implementation is maintained by careful formulation of the automata and by judicious exploration techniques. Results are presented for traditionally referenced benchmarks, several large synthetic benchmarks, and a practical industrial example.