Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
VLSI Signal Processing; A Bit-Serial Approach
VLSI Signal Processing; A Bit-Serial Approach
Scheduling for functional pipelining and loop winding
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Estimation of lower bounds in scheduling algorithms for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An effective methodology for functional pipelining
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Automata-Based Symbolic Scheduling for Looping DFGs
IEEE Transactions on Computers
On applicability of symbolic techniques to larger scheduling problems
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Exact scheduling strategies based on bipartite graph matching
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
PHIDEO: a silicon compiler for high speed algorithms
EURO-DAC '91 Proceedings of the conference on European design automation
Highly flexible multi-mode system synthesis
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
EURASIP Journal on Applied Signal Processing
A Methodology for Rapid Optimization of HandelC Specifications
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
An optimization approach to the synthesis of multichip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a pipelined datapath synthesis system for digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a new algorithm for the generation of pipelined designs developed for use in an interactive behavioural synthesis system. Our technique uses a novel iterative optimisation algorithm that allows the user to trade-off interactive response time with solution quality. Two examples are given to demonstrate the effectiveness of our approach. These provide comparisons with (i) an expert designer and (ii) recently published algorithms for pipeline synthesis.