Design of a pipelined datapath synthesis system for digital signal processing

  • Authors:

  • Hong-Shin Jun;Sun-Young Hwang

  • Affiliations:

  • Department of Electronic Engineering, Sogang University, Seoul, Korea;Department of Electronic Engineering, Sogang University, Seoul, Korea

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 1994

Quantified Score

Hi-index 0.00

Visualization

Abstract

In this paper, we describe the design of SODASDSP (Sogang Design Automation System-DSP), a pipelined datapath synthesis system targeted for application-specific DSP chip design. Through facilitated user interaction, the design space of pipeliied datapaths for given design descriptions can be explored to produce an optimal design which meets design constraints. Taking SFG (Signal Flow Graph) in schematic as inputs, SODAS-DSP generates pipelined datapaths through scheduling and module allocation processes. New scheduling and module allocation algorithms are proposed for efficient synthesis of pipelined hardwares. The proposed scheduling algorlthm is of iterativelconstructive nature, where the measure of equidistribution of operations among pipeline partitions is adopted as the objective function. Module allocation is performed in two passes: the first pass for initial allocation and the second one for reduction of interconnection cost. In the experiments, we compare the synthesis results for benchmark examples with those of recent pipelined datapath synthesis systems, Sehwa and PISYN, and show the effectiveness of SODAS-DSP.