Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A new approach to pipeline optimisation
EURO-DAC '90 Proceedings of the conference on European design automation
An area estimation methodology for FPGA based designs at systemc-level
Proceedings of the 41st annual Design Automation Conference
Time-constrained scheduling of large pipelined datapaths
Journal of Systems Architecture: the EUROMICRO Journal
Codesign of a Computationally Intensive Problem in GF(3)
RSP '07 Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping
A Handel-C Implementation of a Computationally Intensive Problem in GF(3)
ENICS '08 Proceedings of the 2008 International Conference on Advances in Electronics and Micro-electronics
Automatic Identification of Parallelism in Handel-C
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Sehwa: a software package for synthesis of pipelines from behavioral specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel FPGA-based implementation of scatter search
Proceedings of the 12th annual conference on Genetic and evolutionary computation
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Utilizing high level hardware description languages for the creation of customized circuits facilitates the rapid development and deployment of new hardware. While hardware design languages increase the speed at which hardware can be developed, creating hardware designs that are both efficient in resource usage and processing speed can be time consuming and require much experience. This problem is compounded more by the long design cycle times that are introduced by the long compilation and synthesis times that are required to translate a high level hardware description language to a circuit. This problem is addressed by performing some of the optimizations automatically, pre-synthesis, reducing the total number of synthesis cycles that are required, saving much development time.