Theory of linear and integer programming
Theory of linear and integer programming
Constrained resource sharing and conflict resolution in Hebe
Integration, the VLSI Journal
Rotation scheduling: a loop pipelining algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
High-level synthesis scheduling and allocation using genetic algorithms
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An integrated algorithm for memory allocation and assignment in high-level synthesis
Proceedings of the 39th annual Design Automation Conference
High-level synthesis of multiple-precision circuits independent of data-objects length
Proceedings of the 39th annual Design Automation Conference
High Level Synthesis of Pipelined Datapaths
High Level Synthesis of Pipelined Datapaths
CALiBeR: a software pipelining algorithm for clustered embedded VLIW processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A super-scheduler for embedded reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Exact scheduling strategies based on bipartite graph matching
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Representing and Scheduling Looping Behavior Symbolically
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
An Approach to High-Level Synthesis Using Constraint Logic Programming
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Algorithmic aspects of hardware/software partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Behavioral optimization using the manipulation of timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Methodology for Rapid Optimization of HandelC Specifications
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Evaluating the Kernighan-Lin Heuristic for Hardware/Software Partitioning
International Journal of Applied Mathematics and Computer Science
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This paper addresses the most crucial optimization problem of high-level synthesis: scheduling. A formal framework is described that was tailored specifically for the definition and investigation of the time-constrained scheduling problem of pipelined datapaths. Theoretical results are presented on the complexity of the problem. Moreover, two new heuristic algorithms are introduced. The first one is a genetic algorithm, which, unlike previous approaches, searches the space of schedulings directly. The second algorithm realizes a heuristic search using constraint logic programming methods. The performance of the proposed algorithms has been evaluated on a set of benchmarks and compared to previous approaches.