Parallel FPGA-based implementation of scatter search

Authors:
Maxwell Walton;Gary Grewal;Gerarda Darlington
Affiliations:
University of Guelph, Guelph, ON, Canada;University of Guelph, Guelph, ON, Canada;University of Guelph, Guelph, ON, Canada
Venue:
Proceedings of the 12th annual conference on Genetic and evolutionary computation
Year:
2010

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Abstract

Scatter Search [1] is an effective and established population-based meta-heuristic that has been used to solve a variety of hard optimization problems. However, like most population-based meta-heuristics, the time required to find high-quality solutions can become prohibitive as problem sizes grow. In this paper, we present a hardware implementation of scatter search on a Field-Programmable Gate-Array (FPGA). Our objective is to improve the runtime of scatter search by exploiting the potentially massive performance benefits that are available through the native parallelism in hardware. When implementing scatter search we employ Handel-C [2] - a programming language specifically designed to enable software developers to easily synthesize C-like programs into synchronous hardware. As far as we know, this is the first time that scatter search has been implemented in hardware (of any form). Our empirical results show that by effectively exploiting data parallelism and pipelining a 28x speedup over software can be achieved.