HGA: a hardware-based genetic algorithm
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Acceleration of an FPGA router
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Genetic Algorithms: Principles and Perspectives: A Guide to GA Theory
Genetic Algorithms: Principles and Perspectives: A Guide to GA Theory
Implementing a genetic algorithm on a parallel custom computing machine
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Compact FPGA-based True and Pseudo Random Number Generators
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
The Design Warrior's Guide to FPGAs
The Design Warrior's Guide to FPGAs
Evolutionary Computation - Special issue on magnetic algorithms
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
Parallel FPGA-based implementation of scatter search
Proceedings of the 12th annual conference on Genetic and evolutionary computation
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During the last decade, the complexity and size of circuits have been rapidly increasing, placing a stressing demand on industry for faster and more efficient CAD tools for VLSI circuit layout. One major problem is the computational requirements for optimizing the place and route operations of a VLSI circuit. Thus, this paper investigates the feasibility of using reconfigurable computing platforms to improve the performance of CAD optimization algorithms for the VLSI circuit partitioning problem. The proposed Genetic algorithm architecture achieves up-to 5x speedup over conventional software implementation while maintaining on average 88% solution quality. Furthermore, a reconfigurable computing based Hybrid Memetic algorithm improves upon this solution while using a fraction of the execution time required by the conventional software based approach.