Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
High-performance hardware design and implementation of genetic algorithms
Hardware implementation of intelligent systems
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
A hardware Memetic accelerator for VLSI circuit partitioning
Computers and Electrical Engineering
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Abstract: Genetic algorithms (GAs) are a currently popular method for nonlinear optimization that can be used to provide a solution for the chip partitioning problem. Unfortunately, GAs usually require prohibitively large computation times on current workstations. This paper demonstrates the utility of the Armstrong III architecture by addressing the computational problems associated with partitioning large designs using GAs. An example GA is presented for chip partitioning that runs on Armstrong III. GA computation bottlenecks are identified and hardware implementation strategies are discussed. Results are presented that show the Armstrong III architecture can be adapted to execute a GA in significantly less time than current workstations.