Using genetic algorithms to solve NP-complete problems
Proceedings of the third international conference on Genetic algorithms
Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
A FIELD-PROGRAMMABLE PROTOTYPING BOARD: XC4000 BORG USER''S GUIDE
A FIELD-PROGRAMMABLE PROTOTYPING BOARD: XC4000 BORG USER''S GUIDE
Genetic algorithm accelerator GAA-II
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Hardware implementation of intelligent systems
Hardware implementation of intelligent systems
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
High Speed Hardware Computation of Co-evolution Models
ECAL '99 Proceedings of the 5th European Conference on Advances in Artificial Life
Hardware architecture for genetic algorithms
IEA/AIE'2005 Proceedings of the 18th international conference on Innovations in Applied Artificial Intelligence
Development of a customized processor architecture for accelerating genetic algorithms
Microprocessors & Microsystems
A hardware Memetic accelerator for VLSI circuit partitioning
Computers and Electrical Engineering
Hardware implementation of a novel genetic algorithm
Neurocomputing
Real-time machine learning in embedded software and hardware platforms
International Journal of Intelligent Systems Technologies and Applications
Crossover operation engine considering character inheritance
ACACOS'08 Proceedings of the 7th WSEAS International Conference on Applied Computer and Applied Computational Science
FPGA Implementation of Genetic Algorithm for UAV Real-Time Path Planning
Journal of Intelligent and Robotic Systems
Dedicated hardware for inheritance-oriented crossover operation
WSEAS Transactions on Circuits and Systems
Hardware accelerator for evolutionary robotics
WSEAS Transactions on Circuits and Systems
Implementation of a genetic algorithm on a virtex-ii pro FPGA
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Genetic-based machine learning using hardware accelerator
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
High-speed FPGA-based implementations of a genetic algorithm
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine
IEEE Transactions on Evolutionary Computation
Dedicated hardware for scheduling problems using genetic algorithm
AEE'06 Proceedings of the 5th WSEAS international conference on Applications of electrical engineering
Mesh routing topologies for multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Challenges of evolvable hardware: past, present and the path to a promising future
Genetic Programming and Evolvable Machines
Optimization of single variable functions using complete hardware evolution
Applied Soft Computing
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
A genetic algorithm for finding a path subject to two constraints
Applied Soft Computing
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A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders of magnitude have been observed when frequently used software routines were implemented in hardware by way of reprogrammable field-programmable gate arrays (FPGAs). Reprogrammability is essential in a general-purpose GA engine because certain GA modules require changeability (e.g. the function to be optimized by the GA). Thus a hardware-based GA is both feasible and desirable. A fully functional hardware-based genetic algorithm (the HGA) is presented here as a proof-of-concept system. It was designed using VHDL to allow for easy scalability. It is designed to act as a coprocessor with the CPU of a PC. The user programs the FPGAs which implement the function to be optimized. Other GA parameters may also be specified by the user. Simulation results and performance analyses of the HGA are presented. A prototype HGA is described and compared to a similar GA implemented in software. In the simple tests, the prototype took about 6% as many clock cycles to run as the software-based GA. Further suggested improvements could realistically make the HGA 2–3 orders of magnitude faster than the software-based GA.