High Speed Hardware Computation of Co-evolution Models

Authors:
Yoshiki Yamaguchi;Tsutomu Maruyama;Tsutomu Hoshino
Affiliations:
-;-;-
Venue:
ECAL '99 Proceedings of the 5th European Conference on Advances in Artificial Life
Year:
1999

Citing 3
Cited 0

HGA: a hardware-based genetic algorithm

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A Field-Programmable Gate-Array System for Evolutionary Computation

FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
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Evolutionary Computation

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Abstract

Field Programmable Gate Arrays (FPGAs) can provide the most suitable circuits for given problems by reconfiguring its circuits. In this paper, we show that a FPGA chip can achieve about 120 times of speedup compared with a workstation (Ultra-Sparc 200 MHz) in the computation of a co-evolution of strategies and scores in Iterated Prisoner's Dilemma game. This speedup makes it possible to challenge more complex problems beyond the limitation by software.