Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
HGA: a hardware-based genetic algorithm
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Genetic algorithms + data structures = evolution programs (3rd ed.)
Genetic algorithms + data structures = evolution programs (3rd ed.)
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
A Hardware Implementation of a Genetic Programming System Using FPGAs and Handel-C
Genetic Programming and Evolvable Machines
Uniform Crossover in Genetic Algorithms
Proceedings of the 3rd International Conference on Genetic Algorithms
Synthesis of a Systolic Array Genetic Algorithm
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
An analysis of the behavior of a class of genetic adaptive systems.
An analysis of the behavior of a class of genetic adaptive systems.
A hardware pipeline for function optimization using genetic algorithms
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
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In this paper, a new programmable RISC processor architecture named VGP-I is proposed, aiming to the acceleration of genetic algorithms in embedded systems. Compared to other GA engines, the VGP-I specification defines a compact instruction set supporting multiple operator types, with scalable instruction encodings, programmer-visible and auxiliary registers and optional extensions. Apart from the programmable accelerator approach, VGP-I instructions have been tightly integrated to the Nios II soft-core processor as well. For performance assessment, a cycle-accurate reference VGP-I model has been developed while VGP-I subsets have been realized on a prototype microarchitecture and as Nios II custom instructions, both verified on programmable logic. Performance improvements on the execution of genetic operators are typically at the level of two orders of magnitude with application kernels written in ANSI C being accelerated by about 20x due to the usage of GA instruction set extensions.