An efficient problem-independent hardware implementation of genetic algorithms

Authors:
Nadia Nedjah;Luiza de Macedo Mourelle
Affiliations:
Department of Electronics Engineering and Telecommunications, Faculty of Engineering, State University of Rio de Janeiro, Brazil;Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Brazil
Venue:
Neurocomputing
Year:
2007

Citing 4
Cited 5

HGA: a hardware-based genetic algorithm

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Stochastic Neural Computation I: Computational Elements

IEEE Transactions on Computers
Synthesis of a Systolic Array Genetic Algorithm

IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron

IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods

Design of a reconfigurable pseudorandom number generator for use in intelligent systems

Neurocomputing
Preference-based multi-objective evolutionary algorithms for power-aware application mapping on NoC platforms

Expert Systems with Applications: An International Journal
An FPGA implementation of the SMG-SLAM algorithm

Microprocessors & Microsystems
An efficient crossover architecture for hardware parallel implementation of genetic algorithm

Neurocomputing
HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems

Computing

Quantified Score

Hi-index	0.01

Visualization

Abstract

In this paper, we propose a massively parallel architecture for hardware implementation of genetic algorithms. This design is quite innovative as it provides a viable solution to the fitness computation problem, which depends heavily on the problem-specific knowledge. The proposed architecture is completely independent of such specifics. It implements the fitness computation using a neural network. The hardware implementation of the used neural network is stochastic and thus minimise the required hardware area without much increase in response time. Last but not least, we demonstrate the characteristics of the proposed hardware and compare it to existing ones.