Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron

Authors:
Nadia Nedjah;Luiza Macedo Mourelle
Affiliations:
Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Rio de Janeiro, Brazil;Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Rio de Janeiro, Brazil
Venue:
IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods
Year:
2009

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Abstract

In this paper, we propose reconfigurable, low-cost and readily available hardware architecture for an artificial neuron. This is used to build a feed-forward artificial neural network. For this purpose, we use field- programmable gate arrays i.e. FPGAs. However, as the state-of-the-art FPGAsstill lack the gate density necessary to the implementation of large neural networks of thousands of neurons, we use a stochastic process to implement the computation performed by a neuron. The multiplication an addition of stochastic values is simply implemented by an ensemble of XNORand ANDgates respectively.